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3.3V DRAM Modules 144 pin SO-DIMM EDO-DRAM Modules 8MB , 16MB, 32MB & 64MB density
HYM64Vx005GCD(L)-60
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144 Pin JEDEC Standard, 8 Byte Small Outline Dual In-line Memory Modules with 8 Byte busses for PC notebook applications Chip-on Board (COB) Assembly Technique One bank 1M x 64, 2M x 64, 4M x 64 and 8M x 64 non-parity module organisations Performance:
-60 tRAC tCAC tAA tRC tHPC RAS Access Time CAS Access Time Access Time from Address Cycle Time EDO Mode Cycle Time 60 ns 15 ns 30 ns 104 ns 25 ns
* * *
* * * * * * *
Single +3.3V( 0.3V ) power supply CAS-before-RAS refresh, RAS-only-refresh L-versions use low power DRAMs and support Self Refresh ( leep mode" s ) Decoupling capacitors mounted on substrate All inputs, outputs are LVTTL compatible Optional serial presence detect Gold contact pad
Semiconductor Group
1
12.97
HYM64Vx005GCD(L)-60 144 pin SODIMM-Modules
These SIEMENS modules are industry standard 144-pin 8-byte EDO-DRAM Small Outline Dual Inline Memory Modules (SO-DIMM) which are organised as x 64 high speed memory arrays designed for use in non-parity applications. These SO-DIMMs are assemble in Chip-On-Board (COB) assembly technique. L-versions support low power DRAMs with Self Refresh ( leep mode" s ) These modules use serial presence detects implemented via a serial E 2PROM using the two pin I 2C protocol. This communication protocol uses CLOCK (SCL) and DATA I/O (SDA) lines to synchronously clock data between the master and the slave E 2PROM device. The device address for the E 2PROM is set to zero at the module. The first 128 bytes are utilized by the SODIMM manufacturer and the second 128 bytes are available to the end user. All SIEMENS 144-pin SO-DIMMs provide a high performance, flexible 8-byte interface in a 67,5 mm long footprint with 25,4 mm height.
Product Spectrum:
Standard versions:
DRAMs used 4 1Mx16 8 2Mx8 4 4Mx16 8 8Mx8 Rows 10 11 12 12 Columns 10 10 10 11 Refresh 1k 2k 4k 4k Period 16 ms 32 ms 64 ms 64 ms
1M x 64 2M x 64 4M x 64 8M x 64
HYM64V1005GCD-60 HYM64V2005GCD-60 HYM64V4005GCD-60 HYM64V8005GCD-60
Low Power Versions with Self Refresh:
DRAMs used 4 1Mx16 8 2Mx8 4 4Mx16 8 8Mx8 Rows 10 11 12 12 Columns 10 10 10 11 Refresh 1k 2k 4k 4k Period 128 ms 128 ms 128 ms 128 ms
1M x 64 2M x 64 4M x 64 8M x 64
HYM64V1005GCDL-50/-60 HYM64V2005GCDL-50/-60 HYM64V4005GCDL-50/-60 HYM64V8005GCDL-50/-60
Card Dimensions:
Organisation 1M x 64 2M x 64 4M x 64 8M x 64 PCB-Board L-DIM-144-C1 L-DIM-144-C2 L-DIM-144-C3 L-DIM-144-C4 L x H x T [mm] 67.60 x 25.40 x 3.80 67.60 x 25.40 x 3.80 67.60 x 25.40 x 3.80 67.60 x 25.40 x 3.80
Semiconductor Group
2
HYM64Vx005GCD(L)-60 144 pin-SODIMM-Modules
Pin Names A0-Ax DQ0 - DQ63 RAS0 CAS0 - CAS7 WE OE Vcc Vss SCL SDA N.C. Address Inputs Data Inout/Output Row Address Strobe Column Address Strobe Read / Write Input Output Enable Power (+3.3 Volt) Ground Clock for Presence Detect Serial Data Out for Presence Detect No Connection
Capacitance TA = 0 to 70 C; VCC = 3.3 V 0.3 V; f = 1 MHz Parameter Input capacitance (Addresses) Input capacitance (RAS0) Input capacitance (CAS0-CAS7) Input capacitance (WE, OE) I/O capacitance (DQ0-DQ63) Input Capacitance (SCL) Input/Output capacitance (SDA) Symbol Limit Values 2M x 64 4Mx64 25 22 8 20 9 8 10 pF pF pF pF pF pF pF 32 32 10 32 8 8 10 Unit
CI1 CI2 CI3 CI4 CIO1
Cscl Csda
Semiconductor Group
3
HYM64Vx005GCD(L)-60 144 pin SODIMM-Modules
Pin Configuration
PIN # Front Side VSS DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 Vss CAS0 CAS1 Vcc A0 A1 A2 Vss DQ8 DQ9 DQ10 DQ11 Vcc DQ12 DQ13 DQ14 DQ15 Vss NC NC DU Vcc DU WE RAS0 NC PIN # Back Side VSS DQ32 DQ33 DQ34 DQ35 Vcc DQ36 DQ37 DQ38 DQ39 Vss CAS4 CAS5 Vcc A3 A4 A5 Vss DQ40 DQ41 DQ42 DQ43 Vcc DQ44 DQ45 DQ46 DQ47 Vss NC NC DU Vcc DU NC NC NC PIN # Front Side OE Vss NC NC Vcc DQ16 DQ17 DQ18 DQ19 Vss DQ20 DQ21 DQ22 DQ23 Vcc A6 A8 Vss A9 A10 Vcc CAS2 CAS3 Vss DQ24 DQ25 DQ26 DQ27 Vcc DQ28 DQ29 DQ30 DQ31 Vss SDA Vcc PIN # Back Side NC Vss NC NC Vcc DQ48 DQ49 DQ50 DQ51 Vss DQ52 DQ53 DQ54 DQ55 Vcc A7 A11 Vss (A12) (A13) Vcc CAS6 CAS7 Vss DQ56 DQ57 DQ58 DQ59 Vcc DQ60 DQ61 DQ62 DQ63 Vss SCL Vcc
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72
73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143
74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144
Semiconductor Group
4
HYM64Vx005GCD(L)-60 144 pin-SODIMM-Modules
RAS0 WE OE OE CAS0 DQ0-DQ7 WE RAS CAS4 DQ32-DQ39 OE WE RAS
LCAS I/O1-I/O8
LCAS I/O1-I/O8
CAS1 DQ8-DQ15
UCAS I/O9-I/O16
CAS5 DQ40-DQ47
UCAS I/O9-I/O16
D1
OE CAS2 DQ16-DQ23 WE RAS CAS6 DQ48-DQ55 OE WE
D3
RAS
LCAS I/O1-I/O8
LCAS I/O1-I/O8
CAS3 DQ24-DQ31
UCAS I/O9-I/O16
CAS7 DQ56-DQ63
UCAS I/O9-I/O16
D2
D4
A0-Ax VCC
D1,D2,D3,D4
E2PROM (256wordx8bit) SA0 SA1 SA2
C1-C4 VSS
SCL SDA
Block Diagram for 1M x 64 and 4M x 64 SODIMM modules
Semiconductor Group
5
HYM64Vx005GCD(L)-60 144 pin SODIMM-Modules
RAS0 WE0 OE0 CAS0 DQ0-DQ7 CAS1 DQ8-DQ15 CAS2 DQ16-DQ23 CAS3 DQ24-DQ31 I/O1-I/O8 D3 D1-D7 I/O1-I/O8 D2 CAS7 DQ56-DQ63 I/O1-I/O8 D7 E2PROM (256wordx8bit) SA0 SA1 SA2 I/O1-I/O8 D1 CAS6 DQ48-DQ55 I/O1-I/O8 D6 I/O1-I/O8 D0 CAS5 DQ40-DQ47 I/O1-I/O8 D5 CAS4 DQ32-DQ39 I/O1-I/O8 D4
A0-Ax VCC
C0-C7 VSS
SCL SDA
Block DIagram for 2M x 64 and 8M x 64 SODIMM modules
Semiconductor Group
6
HYM64Vx005GCD(L)-60 144 pin-SODIMM-Modules
TRUTH TABLE
FUNCTION Standby Read Early-Write Late-Write Read-Modify-Write (RMW) EDO Page Mode Read 1st Cycle 2nd Cycle EDO Page Mode Write 1st Cycle 2nd Cycle EDO Page Mode RMW 1st Cycle 2st Cycle RAS only refresh CAS-before-RAS refresh Hidden Refresh READ WRITE Self Refresh
RAS H L L L L L L L L L L L H-L L-H-L L-H-L H-L
CAS X L L L L H-L H-L H-L H-L H-L H-L H L L L L
WRITE X H L H-L H-L H H L L H-L H-L X H H L H
OE X L X H L-H L L X X L-H L-H X X L X X
ROW ADDR X ROW ROW ROW ROW ROW n/a ROW n/a ROW n/a ROW X ROW ROW X
COL ADDR X COL COL COL COL COL COL COL COL COL COL n/a n/a COL COL X
DQ0-DQ63 High Impedance Data Out Data In Data In Data Out, Data In Data Out Data Out Data In Data In Data Out, Data In Data Out, Data In High Impedance High Impedance Data Out Data In High Impedance
Semiconductor Group
7
HYM64Vx005GCD(L)-60 144 pin SODIMM-Modules
Absolute Maximum Ratings Operating temperature range ......................................................................................... 0 to + 70 C Storage temperature range...................................................................................... - 55 to + 125 C Input/output voltage .............................................................................. -0.5 to min (Vcc+0.5, 4.6) V Power supply voltage.................................................................................................... -0.5 to 4.6 V Power dissipation.................................................................................................................. 3.68 W Data out current (short circuit) ................................................................................................ 50 mA Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC Characteristics TA = 0 to 70 C, VSS = 0 V, VCC = 3.3 V 0.3 V Parameter Input high voltage Input low voltage Output high voltage (LVTTL) Output "level voltage (Iout = -2mA) H Output low voltage (LVTTL) Output "evel voltage (Iout = +2mA) Ll Output high voltage (LVCMOS) Output "level voltage (Iout = -100uA) H Ouput low voltage (LVCMOS) Output " level voltage (Iout = +100uA) L Input leakage current,any input
(0 V < Vin < Vcc , all other pins = 0 V
Symbol
Limit Values min. max. Vcc+0.3 0.8 - 0.4 0.2 10 10 2.0 - 0.3 2.4 - Vcc-0.2 -10 - 10
Unit Note V V V V V V A A 1) 1)
VIH VIL VOH VOL VOH VOL II(L) IO(L)
Output leakage current
(DO is disabled, 0 V < Vout < Vcc )
Semiconductor Group
8
HYM64Vx005GCD(L)-60 144 pin-SODIMM-Modules
AC Characteristics 5)6) TA = 0 to 70 C,VCC = 3.3 V 0.3V , tT = 2 ns Parameter
Symbol
16E
Limit Values -60 min. max. - - 10k 10k - - - - 45 30 - - - 50
Unit Note
common parameters
Random read or write cycle time RAS precharge time RAS pulse width CAS pulse width Row address setup time Row address hold time Column address setup time Column address hold time RAS to CAS delay time RAS to column address delay RAS hold time CAS hold time CAS to RAS precharge time Transition time (rise and fall) tRC tRP tRAS tCAS tASR tRAH tASC tCAH tRCD tRAD tRSH tCSH tCRP tT 104 40 60 10 0 10 0 10 14 12 15 50 5 1 ns ns ns ns ns ns ns ns ns ns ns ns ns ns 7
Read Cycle
Access time from RAS Access time from CAS Access time from column address OE access time Column address to RAS lead time Read command setup time Read command hold time Read command hold time referenced to RAS CAS to output in low-Z Output buffer turn-off delay Output turn-off delay from OE Data to CAS low delay tRAC tCAC tAA tOEA tRAL tRCS tRCH tRRH tCLZ tOFF tOEZ tDZC - - - - 30 0 0 0 0 0 0 0 60 15 30 15 - - - - - 15 15 - ns ns ns ns ns ns ns ns ns ns ns ns 11 11 8 12 12 13 8, 9 8, 9 8,10
Semiconductor Group
9
HYM64Vx005GCD(L)-60 144 pin SODIMM-Modules
AC Characteristics (cont' 5)6) d) TA = 0 to 70 C,VCC = 3.3 V 0.3V , tT = 2 ns Parameter
Symbol
16E
Limit Values -60 min. max. - - -
Unit Note
Data to OE low delay CAS high to data delay OE high to data delay
tDZO tCDD tODD
0 13 13
ns ns ns
13 14 14
Write Cycle
Write command hold time Write command pulse width Write command setup time Write command to RAS lead time Write command to CAS lead time Data setup time Data hold time tWCH tWP tWCS tRWL tCWL tDS tDH 10 10 0 15 15 0 10 - - - - - - - ns ns ns ns ns ns ns 16 16 15
Read-modify-Write Cycle
Read-write cycle time RAS to WE delay time CAS to WE delay time Column address to WE delay time OE command hold time tRWC tRWD tCWD tAWD tOEH 138 77 32 47 13 - - - - - ns ns ns ns ns 15 15 15
Hyper Page Mode (EDO) Cycle
Hyper page mode (EDO) cycle time CAS precharge time Access time from CAS precharge Output data hold time RAS pulse width in EDO mode CAS precharge to RAS Delay OE setup time prior to CAS tHPC tCP tCPA tCOH tRAS tRHCP tOES 25 10 - 3 60 32 5 - - 32 - 200k - - ns ns ns ns ns ns 5 - 7
Semiconductor Group
10
HYM64Vx005GCD(L)-60 144 pin-SODIMM-Modules
AC Characteristics (cont' 5)6) d) TA = 0 to 70 C,VCC = 3.3 V 0.3V , tT = 2 ns Parameter
Symbol
16E
Limit Values -60 min. max.
Unit Note
Hyper Page Mode (EDO) Read-modify-Write Cycle
Hyper page mode (EDO) read-write cycle time CAS precharge to WE tPRWC tCPWD 68 49 - - ns ns
CAS-before-RAS refresh cycle
CAS setup time CAS hold time RAS to CAS precharge time Write to RAS precharge time Write hold time referenced to RAS tCSR tCHR tRPC tWRP tWRH 10 10 5 10 10 - - - - - ns ns ns ns ns
CAS-before-RAS counter test cycle
CAS precharge time tCPT 40 - ns
Self Refresh Cycle (L-versions only)
RAS pulse width RAS precharge CAS hold time tRASS tRPS tCHS 100k 110 -50 _ _ _ ns ns ns 17 17 17
Semiconductor Group
11
HYM64Vx005GCD(L)-60 144 pin SODIMM-Modules
Notes:
1) 2) 3) 4) All voltages are referenced to VSS. ICC1, ICC3, ICC4 and ICC6 depend on cycle rate. ICC1 and ICC4 depend on output loading. Specified values are obtained with the output open.
Address can be changed once or less while RAS = Vil. In case of ICC4 it can be changed once or less during a hyper page mode (EDO) cycle 5) An initial pause of 200 s is required after power-up followed by 8 RAS cycles of which at least one cycle has to be a refresh cycle, before proper device operation is achieved. In case of using the internal refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 6) AC measurements assume tT = 2 ns. 7) VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Transition times are also measured between VIH and VIL. 8) Measured with a load equivalent to 1 TTL loads and 100 pF, (Vol = 0.8 V and Voh = 2.0 V). 9) Operation within the tRCD (max.) limit ensures that tRAC (max.) can be met. tRCD (max.) is specified as a reference point only. If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled by tCAC. 10) Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled by tAA. 11) Either tRCH or tRRH must be satisfied for a read cycle. 12) tOFF (max.), tOEZ (max.) define the time at which the output achieves the open-circuit conditions and are not referenced to output voltage levels. tOFF is referenced from the rising edge of RAS or CAS, whichever occurs last. 13) Either tDZC or tDZO must be satisfied. 14) Either tCDD or tODD must be satisfied. 15) tWCS , tRWD , tCWD and tAWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS > tWCS (min.) , the cycle is an early write cycle and data out pin will remain open-circuit (high impedance) through the entire cycle; if tRWD > tRWD (min.) , tCWD > tCWD (min.) and tAWD > tAWD (min.) , the cycle is a read-write cycle and I/O will contain data read from the selected cells. If neither of the above sets of conditions is satisfied, the condition of I/O (at access time) is indeterminate. 16) These parameters are referenced to the CAS leading edge in early write cycles and to the WE leading edge in read-write cycles. 17)When using Self Refresh mode, the following refresh operations must be performed to ensure proper DRAM operation: If row addresses are being refreshed on an evenly distributed manner over the refresh interval using CBR refresh cycles, then only one CBR cycle must be performed immediately after exit from Self Refresh. If row addresses are being refreshed in any other manner (ROR - Distributed/Burst; or CBR-Burst) over the refresh interval, then a full set of row refreshes must be performed immediately before entry to and immediately after exit from Self Refresh
Semiconductor Group
12
HYM64Vx005GCD(L)-60 144 pin-SODIMM-Modules
Serial Presence Detects: A serial presence detect storage device -- E 2PROM is assembled on to the module. Information about the modul confuguration, speed, etc. is written into the EEPROM device during module production using a serial presence detect protocol ( I 2C synchronous 2-wire bus). Standard Version (without Self Refresh & Low Power)
Byte# Description SPD Entry Value Hex HYM 64 V1005 GC-60 80 08 02 0A 0A 01 40 00 01 3C 0F 00 00 10 00 FF FF FF 01 FF FF 64 V2005 GC-60 80 08 02 0B 0A 01 40 00 01 3C 0F 00 00 08 00 FF FF FF 01 06 FF FF 64 V4005 GC-60 80 08 02 0C 0A 01 40 00 01 3C 0F 02 00 10 00 FF FF FF 01 0F FF FF 64 V8005 GC-60 80 08 02 0C 0B 01 40 00 01 3C 0F 02 00 08 00 FF FF FF 01 FF FF
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15-31 32 33-61
Number of SPD bytes Total bytes in Serial PD Memory Type Number of Row Addresses Number of Column Addresses Number of DIMM Banks Module Data Width Module Data Width (cont' d) Module Interface Levels RAS access time CAS access time Dimm Config (Error Det/Corr.) Refresh Rate/Type
128 256 EDO
1 x64 0 LVTTL 60 ns 15 ns none normal 15.6s none NA NA Rev. 1.0
Primary DRAM data width Error checking DRAM data width reserved for future offerings Superset Memory Type Superset information (may be used in future) 62 SPD Revision Designator 63 Checksum for bytes 0-62 64-127 Manufacturer Information (optional) 128- Unused Storage Locations 255
Semiconductor Group
13
HYM64Vx005GCD(L)-60 144 pin SODIMM-Modules
Low Power Version with Self Refresh:
Byte# Description SPD Entry Value Hex HYM 64 64 64 64 V1005 V2005 V4005 V8005 GCL-60 GCL-60 GCL-60 GCL-60 128 80 80 80 80 256 08 08 08 08 EDO 02 02 02 02 0A 0B 0C 0C 0A 0A 0A 0B 1 01 01 01 01 x64 40 40 40 40 0 00 00 00 00 LVTTL 01 01 01 01 60 ns 3C 3C 3C 3C 15 ns 0F 0F 0F 0F none 00 00 02 02 self refresh 85 84 83 83 10 00 FF FF FF 01 FF FF 08 00 FF FF FF 01 FF FF 10 00 FF FF FF 01 FF FF 08 00 FF FF FF 01 FF FF
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15-31 32 33-61
Number of SPD bytes Total bytes in Serial PD Memory Type Number of Row Addresses Number of Column Addresses Number of DIMM Banks Module Data Width Module Data Width (cont' d) Module Interface Levels RAS access time CAS access time Dimm Config (Error Det/Corr.) Refresh Rate/Type
Primary DRAM data width Error checking DRAM data width reserved for future offerings Superset Memory Type Superset information (may be used in future) 62 SPD Revision Designator 63 Checksum for bytes 0-62 64-127 Manufacturer Information (optional) 128- Unused Storage Locations 255
none NA NA Rev. 1.0
Semiconductor Group
14
HYM64Vx005GCD(L)-60 144 pin-SODIMM-Modules
L-DIM-144-C1 to L-DIM-144-C4 SO-DIMM Module package (144 pin, dual read-out, single in-line COB memory module)
Front Side: 3,8
67,5 63,6
4,0
6,0
1 3,3 23.2 24.5
59
61 32.8 4,6 2,5
143
20,0
25.40
1.0 +0.1 -
Backside: 3,7 2 60
O 1,8 62 144
Detail of Contacts: 0.25 max 2.54 min
Details of Notch : 1,5 +/-0,1
+/-0,1
0,8
0,6 +/- 0.05
4,0 2Mx64 COB-SO
DM144-2.WMF
preliminary drawing
Semiconductor Group
15

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